Scott Lerner

Scott Lerner is a PhD student in Electrical Engineering. His research interests include low-power VLSI circuits, modeling of parametric variation, and timing models specifically for clock distribution networks. Scott works under Drexel's Dr. Baris Taskin in the VLSI lab and has done previous research with Dr. Mark Hempstead in the Power Aware Computing lab. His undergraduate research investigated wireless network-on-chip architectures for low-power, high speed communication between a many-core system. Currently, Scott's research is to investigate reducing pessimism by using statistical delay models that allow for an intuitive reduction of constant derating factors. His goal with this research is to develop a methodology for designing resilient hardware based on software workloads. Outside of research, Scott is the Technical Chair of Drexel IEEE Graduate Society and is a teaching assistant for Advanced Programming for Engineers.